Chat with us, powered by LiveChat Latches and flip-flops are considered as sequential circuits and can act ?as data storage devices. In this discussion let’s learn about major ?differences betw - Writingforyou

Latches and flip-flops are considered as sequential circuits and can act ?as data storage devices. In this discussion let’s learn about major ?differences betw

 Latches and flip-flops are considered as sequential circuits and can act  as data storage devices. In this discussion let's learn about major  differences between latches and flipflops. We are also going to discuss  major applications where flipflops are and why. 

 

In your original post, answer the following:

  1. Discuss the difference between latches and flip-flops.
  2. Discuss the applications of flip-flops.

EET 230– Digital Systems II

Multivibrators, Latches and Flip-Flops

Outline of the lecture

2

Sequential Logic

S-R Latch

Gated S-R Latch

D- Latches

Timing Diagrams

Objective of the Lecture

 After successful completion of the lecture students

will be able to:

 State the difference between combinational and sequential

logic.

 Describe the operations of different types of latches and

flip-flops.

 Explain the operation of non-retriggerable and

retriggerable one shot.

 Use logic gates to construct basic latches.

 Draw the timing diagrams for S-R and D-latches.

 Explain the difference between S-R latches and D-latches.

 Recognize the difference between latches and flip-flops. 3

Road Traveled So Far ……….

4

Switches Logic gates Sequential Circuit

Combinational Circuit

?

What is the Sequential Circuit?

5

 Can we build the circuit as shown below?

When the button is pushed: 1) Turn ‘on’ the light if

it is already ‘off’

2) Turn ‘off’ the light if it is already ‘on’

The light should change state within a second of the button press

button light

 What make this circuit so different from those we have discussed before?

1. “State”, i.e., the circuit has memory

2. The input not only change output but also the ‘state’ of the circuit

3. The timing in which the state and output will be changed

6 Sequential = Stateful

(button} (light}

Off On

On Off

1 second timing

What is the Sequential Circuit?

Sequential Logic

 Sequential circuit = Combinational logic + Memory Elements

 Current State of A sequential Circuit: Value stored in memory

elements (value of state variables).

 State transition: A change in the stored values in memory

elements thus changing the sequential circuit from one state to

another state.

7

Combinational

logic

Memory

elements

Combinational

outputs Memory outputs

Inputs

Sequential Logic

 A Memory Element: A logic device that can remember a single-bit value

indefinitely, or change its value on command from its inputs.

 The output Q of the memory element represents the value stored in the

memory element. This is also called the state variable of the memory

elements. A memory element can be in one of two possible states:

 Q = 0 (the memory element has 0 stored), also said be in state 0.

 Q =1 (the memory element has 1 stored), also said to be in state 1.

 The commands to the memory element formed by its input(s) may include:

 Set: Store 1 (Q=1) in the memory element.

 Reset: Store 0 (Q=0) in the memory element.

 Flip: Change stored value from 0 to 1 or from 1 to 0.

 Hold value: Memory value does not change.

8

command Memory

element Memory Element Output:

stored single-bit value

Q

9

Sequential Circuits

 The outputs of a sequential circuit depend on not only the inputs, but also the state, or the current contents of some memory

 This makes things more difficult to understand, since the same inputs can yield different outputs, depending on what’s stored in memory

 The memory contents can also change as the circuit runs

 We’ll some need new techniques for analyzing and designing sequential circuits

Combinational circuit

Inputs

Memory

Outputs

10

Examples of Sequential Devices

 Many real-life devices are sequential in nature:

 Combination locks open if you enter numbers in the right

order

 Elevators move up or down and open or close depending

on the buttons that are pressed on different floors and in

the elevator itself

 Traffic lights may switch from red to green depending on

whether or not a car is waiting at the intersection

11

What Exactly is Memory?

 A memory should have at least three properties.

1. It should be able to hold a value

2. You should be able to read the value that was saved

3. You should be able to change the value that’s saved

 We’ll start with the simplest case, a one-bit memory

1. It should be able to hold a single bit, 0 or 1

2. You should be able to read the bit that was saved

3. You should be able to change the value. Since there’s only a single bit, there are only two choices:  Set the bit to 1

 Reset, or clear, the bit to 0

12

The Basic Idea of Storage

 How can a circuit "remember" anything, when it’s just a bunch of gates that produce outputs according to the inputs?

 The basic idea is to make a loop, so the circuit outputs are also inputs

 Here is one initial attempt, shown with two equivalent layouts:

 Does this satisfy the properties of memory?

 These circuits "remember" Q, because its value never changes (Similarly, Q' never changes either)

 We can also "read" Q, by attaching a probe or another circuit

 But we can’t change Q! There are no external inputs here, so we can’t control whether Q=1 or Q=0

13

The S-R Latch Circuit

 Let’s use NOR gates instead of inverters. The SR latch below has two inputs S and R, which will let us control the outputs Q and Q'

 Here Q and Q' feed back into the circuit. They’re not only outputs, they’re also inputs!

 To figure out how Q and Q' change, we have to look at not only the inputs S and R, but also the current values of Q and Q':

Qnext = (R + Q'current)'

Q'next = (S + Qcurrent)'

 Let’s see how different input values for S and R affect this thing

14

Storing a Value: SR = 00

 What if S = 0 and R = 0?

 The equations on the right reduce to:

Qnext = (0 + Q'current)' = Qcurrent

Q'next = (0 + Qcurrent)' = Q'current

 So when SR = 00, then Qnext = Qcurrent

Whatever value Q has, it keeps

 This is exactly what we need to store values

in the latch

Qnext = (R + Q’current)’ Q’next = (S + Qcurrent)’

15

Setting the Latch: SR = 10

 What if S = 1 and R = 0?

 Since S = 1, Q’next is 0, regardless of Qcurrent:

Q’next = (1 + Qcurrent)’ = 0

 Then, this new value of Q’ goes into the top NOR gate, along with R = 0

Qnext = (0 + 0)’ = 1

 So when SR = 10, then Q’next = 0 and Qnext = 1

 This is how you set the latch to 1. The S input stands for “set”

 Once Qnext becomes 1, the outputs will stop changing. This is a stable state

Qnext = (R + Q’current)’ Q’next = (S + Qcurrent)’

16

Resetting the Latch: SR = 01

 What if S = 0 and R = 1?

 Since R = 1, Qnext is 0, regardless of Qcurrent:

Qnext = (1 + Q’current)’ = 0

 Then, this new value of Q goes into the bottom NOR gate, where S = 0

Q’next = (0 + 0)’ = 1

 So when SR = 01, then Qnext = 0 and Q’next = 1

 This is how you reset, or clear, the latch to 0 The R input stands for “reset”

Qnext = (R + Q’current)’ Q’next = (S + Qcurrent)’

17

SR Latches are Memories!

 This little table shows that our latch provides everything we need in a memory: we can set it, reset it, and remember the current value

 The output Q represents the data stored in the latch. It is sometimes called the state of the latch

 We can expand the table above into a state table, which explicitly shows that the next values of Q and Q’ depend on their current values, as well as on the inputs S and R

S R Q

0 0 No change

0 1 0 (reset)

1 0 1 (set)

Inputs Current Next

S R Q Q’ Q Q’

0 0 0 1 0 1

0 0 1 0 1 0

0 1 0 1 0 1

0 1 1 0 0 1

1 0 0 1 1 0

1 0 1 0 1 0

18

SR Latches are Sequential!

 Notice that for inputs SR = 00, the next value of Q could be either 0 or 1, depending on the current value of Q

 So the same inputs can yield different outputs, depending on whether the latch was previously set or reset

 This is very different from the combinational circuits that we’ve seen so far, where the same inputs always yield the same outputs

Inputs Current Next

S R Q Q’ Q Q’

0 0 0 1 0 1

0 0 1 0 1 0

0 1 0 1 0 1

0 1 1 0 0 1

1 0 0 1 1 0

1 0 1 0 1 0

S R Q

0 0 No change

0 1 0 (reset)

1 0 1 (set)

19

What about SR = 11?

 Both Qnext and Q'next will become 0

 This contradicts the assumption that Q and Q’ are always complements

 Another problem is what happens if we then make S = 0 and R = 0 together

Qnext = (0 + 0)' = 1

Q’next = (0 + 0)' = 1

 But these new values go back into the NOR gates, and in the next step we get:

Qnext = (0 + 1)' = 0

Q’next = (0 + 1)' = 0

 The circuit enters an infinite loop, where Q and Q’ cycle between 0 and 1 forever

 This is actually the worst case, but the moral is don’t ever set SR=11!

Qnext = (R + Q’current)’ Q’next = (S + Qcurrent)’

0

0

0

0

0

0

1

1

20

Converting a NOR S-R to an NAND S-R

Active High NOR

Gate Implementation Push Bubbles

(DeMorgan’s) Rearrange

Bubbles Convert

from Bubbles

to Active Low

Signal Names

S

R Q

Q

S

R Q

Q S

R Q

Q

Q

Q

S

R

21

S’R’ Latch

 There are several varieties of latches

 You can use NAND instead of NOR gates to get a S’R’ latch

 The input signals for the NAND latch are the complement of the signals for the NOR latch, hence the name S’R’ latch

 You can derive this table by writing equations for the outputs in terms of the inputs and the current state, just as we did for the SR latch

S’ R’ Q

1 1 No change

1 0 0 (reset)

0 1 1 (set)

0 0 Avoid!

22

An SR Latch with a Control Input

 Here is an SR latch with a control input C

 Notice the hierarchical design!  The dotted blue box is the S’R’ latch from the previous slide

 The additional NAND gates are simply used to generate the correct inputs for the S’R’ latch

 The control input acts just like an enable. Latch can only change when C = 1, all other times the circuit remains in the same state no matter what values are on the S and R inputs

C S R S’ R’ Q

0 x x 1 1 No change

1 0 0 1 1 No change

1 0 1 1 0 0 (reset)

1 1 0 0 1 1 (set)

1 1 1 0 0 Avoid!

SR Latch with Enable input

23

SR Latch with Enable input

25

D Latch

 The D latch is designed to eliminate the undefined state of the SR latch by ensuring that the S and R inputs are never high at the same time

 A D latch is based on an S'R' latch. The additional gates generate the S' and R' signals, based on inputs D ("Data") and C ("Control")

 When C = 0, S' and R' are both 1, so the state Q does not change

 When C = 1, the latch output Q will equal the input D

 No more messing with one input for set and another input for reset!

 Also, this latch has no "bad" input combinations to avoid. Any of the four possible assignments to C and D are valid

C D Q

0 x No change

1 0 0

1 1 1

D Latch

D Latch

S R Q

0 0 No change

0 1 0 (reset)

1 0 1 (set)

Inputs Current Next

S R Q Q’ Q Q’

0 0 0 1 0 1

0 0 1 0 1 0

0 1 0 1 0 1

0 1 1 0 0 1

1 0 0 1 1 0

1 0 1 0 1 0S’ R’ Q

1 1 No change

1 0 0 (reset)

0 1 1 (set)

0 0 Avoid!

C S R S’ R’ Q

0 x x 1 1 No change

1 0 0 1 1 No change

1 0 1 1 0 0 (reset)

1 1 0 0 1 1 (set)

1 1 1 0 0 Avoid!

C D Q

0 x No change

1 0 0

1 1 1

Latch Timing Diagram Practice

32

Latch Timing Diagram Practice

33

Latch Timing Diagram Practice

34

Latch Timing Diagram Practice

35

Latch Timing Diagram Practice

36

Latch Timing Diagram Practice

37

Summary

38

Sequential Logic

S-R Latch

Gated S-R Latch

D- Latches

Timing Diagrams

,

EET 230– Digital Systems II

Multivibrators, Latches and Flip-

Flops

2

Outline of the lecture

Edge – Triggered S-R Flip-Flop

Method of Edge – Triggering

Edge – Triggered D Flip-Flop

Edge – Triggered J-K Flip-Flop

Asynchronous Preset and Clear Inputs

Flip-Flop Operating Characteristics

Flip-Flop Applications

Objective of the Lecture

 After successful completion of the lecture students

will be able to:

 Explain the operations of S-R, D and J-K flip-flops

 Draw the timing diagram for S-R, D and J-K flip-flops

 Understand the significance of propagation delay.

 Set-up time and hold time in logic circuits

 Explain methods of triggering flip-flops

 Apply flip-flops in basic applications such as square wave

generation and frequency division

3

4

Edge Triggered Flip-Flops

 An edge triggered flip-flop changes state either at the

positive edge (rising edge) or a the negative edge (falling

edge) of the clock pulse

 Its sensitive to inputs only at this transition of the clock

 There are 3 types of edge triggered flips: S-R, D, and J-K

 Each flip-flop can be either positive edge triggered (no

bubble at the C input) or negative edge triggered (bubble at

the C input)

5

Edge Triggered Flip-Flops

 Edge-triggered flip-flop logic symbols (top: positive edge-triggered; bottom: negative edge-triggered)

 The dynamic input indicator means the flip flop changes state only on the edge of a clock pulse

6

A Method of Edge Triggering

 The S-R flip-flop differs from the gated S-R latch only in that it has a pulse transition detector

 This circuit produces a very short duration spike on either the positive- going transition or the negative-going transition of each clock pulse

 The circuit uses a AND gate as the input thereby providing a delay in nanoseconds

 The inverter is used to handle both positive and negative edge triggering because of the inversion process

 The Enable in this case is called the Clock (CLK) S

R

Q

Q'

pulse transition detector

CLK

A simplified logic diagram for an edge-triggered S-R flip flop

7

Edge Detection Circuits

8

Edge Triggered S-R Flip-Flop

 The S and R inputs of the S-R flip-flop are called synchronous inputs because data on these inputs are transferred to the flip-flop’s output only on the triggering edge of the clock pulse

 When the S is HIGH and R is LOW, the Output goes HIGH on the triggering edge of the clock pulse – flip flop is SET

 When the S is LOW and R is HIGH, the Output goes LOW on the triggering edge of the clock pulse – flip flop is RESET

 When both S and R are LOW, the output does not change from its previous state

 An invalid condition exists when both S and R are HIGH

S

R

Q

Q'

pulse transition detector

CLK

9

Operation of a positive edge-triggered S-R flip-flop

 Note: The operation and truth table for a negative edge-triggered flip-flop are the same as those for a positive except that the falling edge of the clock pulse is the triggering edge

S R Q Q* Operation

0 0 Q Q Hold

1 0 1 0 Set (Q → 1)

0 1 0 1 Reset (Q → 0)

1 1 X X Not Allowed

Positive Edge Triggered S-R Flip-Flop Timing Diagram

S R Q Q* Operation

0 0 Q Q Hold

1 0 1 0 Set (Q → 1)

0 1 0 1 Reset (Q → 0)

1 1 X X Not Allowed

Positive Edge Triggered S-R Flip-Flop Timing Diagram

12

Positive Edge Triggered S-R Flip-Flop Timing Diagram

Edge Triggered S-R Flip-Flop Timing Diagram

14

The Edge Triggered D Flip-Flop

 The D flip-flop is useful when a single bit (1 or 0) is to be stored

 The addition of an inverter to an S-R flip flop creates a basic D Flip- Flop

 The flip-flop only has 1 input in addition to the clock

 If there is a HIGH on the D when a clock pulse is applied, the flip flop will set and the HIGH on the D input is stored by the flip-flop on the triggering edge of the clock pulse

 If there is a LOW on the D when the clock pulse is applied, the flip flop will reset and the LOW on the D input is stored by the flip-flop on the triggering edge of the clock pulse

 In a SET state the flip-flop is storing a 1, and the RESET state is storing a 0

A positive edge-triggered D Flip-Flop formed with an S-R flip-flop and an inverter

15

The Positive Edge Triggered D Flip-Flop Timing Diagram

Note: From the above timing diagram, it's called a D flip-flop because it delays the signal. The output is just the input delayed until the next active clock transition

Q*0 0 1 1

D Q C

0 0 0 1 1 0 1 1

Set 0

Set 1

The Positive Edge Triggered D Flip-Flop Timing Diagram

Edge Triggered D Flip-Flop Timing Diagram

18

The Edge Triggered J-K Flip-Flop

 The J-K Flip-Flop is versatile and is a widely used type of

flip flop

 The J and K designations for the inputs have no know

significance except that they adjacent letters in the alphabet

 The function of the J-K flip flop is identical to that of the S-R

flip-flop in the SET, RESET and no change conditions of

operation

 The difference is that the J-K flip-flop has no invalid state as

does the S-R flip-flops

19

The Negative Edge Triggered J-K Flip-Flop Timing Diagram

Q*

0

1

0

0

1

1

1

0

J K Q C

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1 Toggle

Hold

Reset

Set

Q*

0

1

0

0

1

1

1

0

J K Q C

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1 Toggle

Hold

Reset

Set

Edge Triggered J-K Flip-Flop Timing Diagram

Edge Triggered J-K Flip-Flop Timing Diagram

24

Asynchronous Preset and Clear Inputs

 The S-R, D and J-K inputs just discussed are called synchronous inputs because data on these inputs are transferred to the flip-flop’s output only on the triggering edge of the clock pulse → data is transferred synchronously with clock

 Most IC flip flops also have asynchronous inputs